External Bus Interface
13-42 MPC823e REFERENCE MANUAL MOTOROLA
EXTERNAL BUS
13
INTERFACE
The external circuitry can provide TEA when no device responds by asserting TA within an
appropriate period of time after the MPC823e initiates the bus cycle. This allows the cycle
to terminate and the processor to enter exception processing for the error condition.
To properly control termination of a bus cycle for a bus error, TEA
must be asserted
simultaneously or before TA
is asserted. TEA must be negated before the second rising
edge after it was sample-asserted to avoid detecting an error for the next initiated bus cycle.
TEA
is an open-drain pin that allows the wire-OR of any different error generation sources.
13.4.11.1 RETRY SIGNAL. When an external device asserts the RETRY
signal during a
bus cycle, the MPC823e enters a sequence in which it terminates the current transaction,
relinquishes ownership of the bus, and retries the cycle using the same address, address
attributes, and data. Figure 13-28 illustrates the behavior of the MPC823e when the RETRY
signal is detected as a termination of a transfer. The figure illustrates that when the internal
arbiter is enabled, the MPC823e negates the BB
signal and asserts the BG signal in the
clock cycle following retry detection. This allows any external master to gain bus ownership.
In the next clock cycle, a normal arbitration procedure may occur. The figure also shows that
the external master did not use the bus, so the MPC823e initiates a new transfer with the
same address and attributes as before. In Figure 13-29 the same situation is illustrated to
show that the MPC823e is working with an external arbiter. In the clock cycle after the CPU
recognizes that the RETRY
signal is asserted, the BR and BB signals are negated. One
clock cycle later, the normal arbitration procedure may occur. This input signal requires a
pull-up resistor.
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