System Interface Unit
12-28 MPC823e REFERENCE MANUAL MOTOROLA
SYSTEM INTERFACE UNIT
12
12.10 FREEZE OPERATION
When the FRZ signal is asserted, the clocks to the software watchdog, periodic interrupt
timer, real-time clock, timebase counter, and decrementer can be disabled. This is
controlled by the associated bits in the control register of each timer. If they are programmed
to stop counting when FRZ is asserted, the counters maintain their values until FRZ is
negated. The bus monitor, however, will be enabled regardless of this signal’s state.
12.10.1 Low-Power Stop Operation
When the PowerPC core is set in a low-power mode (doze, sleep, deep sleep), the software
watchdog timer is frozen. It remains frozen and maintains its count value until the core exits
this mode and continues to execute instructions. The periodic interrupt timer, decrementer,
and timebase are not influenced by these low-power modes and they continue to run at their
respective frequencies. These timers can generate an interrupt to bring the MPC823e out
of the low-power modes.