PowerPC Architecture Compliance
MOTOROLA MPC823e REFERENCE MANUAL 7-13
PPC ARCHITECTURE
7
COMPLIANCE
SRR1—Save/Restore Register 1
0–3 Set to 0.
4 Set to 1.
10 Set to 1.
11–15 Set to 0.
Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
MSR—Machine State Register
IP No change.
ME No change.
LE Bits are copied from the ILE.
Other Set to 0.
Some instruction TLB registers are set to the values described in
Section 11 Memory Management Unit. Execution resumes at offset x’01100’ from the
base address indicated by MSR
IP
.
7.3.7.3.12 Implementation-Specific Instruction TLB Error Interrupt. This type of
interrupt occurs as a result of one of the following conditions:
• The effective address cannot be translated. Either the segment or page valid bit of this
page is cleared in the translation table.
• The fetch access violates storage protection.
• The fetch access is to guarded storage and MSR
IR
=1.
The following registers are set:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
SRR1—Save/Restore Register 1
1 Set to 1 if the translation of an attempted access is not found in the translation
tables. Otherwise, set to 0.
2 Set to 0.
3 Set to 1 if the fetch access was to a guarded storage when MSR
IR
= 1 or when
bit 4 is set. Otherwise, set to 0.
4 Set to 1 if the storage access is not permitted by the protection mechanism;
otherwise set to 0. In the first revision when this bit is set, Bits 3 and 10 are
also set, but in future revisions this bit may be set alone.
10 Set to 1 when Bit 4 is set. Otherwise, set to 0.
11–15 Set to 0.
Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
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