The PowerPC Core
6-24 MPC823e REFERENCE MANUAL MOTOROLA
CORE
6
6.4.1.3 INITIALIZING THE CONTROL REGISTERS
6.4.1.3.1 System Reset Interrupt. A system reset interrupt occurs when the IRQ0
pin is
asserted. The only control registers affected by the system reset interrupt are the MSR,
SRR0, and SRR1 registers. For information on the values of these registers, refer to
Section 7.3.7.3.1 System Reset Interrupt.
6.4.1.3.2 Hard/Soft Reset. When a hard or soft reset occurs, the registers affected by
system reset are set in the same way. The following list shows how each register is set.
• SRR0, SRR1—Set to an undefined value.
• MSR
IP
—Programmable.
• MSR
ME
—Set to zero.
• ICTRL—Set to 0.
• LCTRL1—Set to 0.
• LCTRL2—Set to 0.
• COUNTA
16-31
—Set to 0.
• COUNTB
16-31
—Set to 0.
• ICR—Set to 0 (no interrupt occurred).
• DER
2,14,28:31
—Set to 1 (all debug-specific interrupts cause debug mode entry).
6.5 THE FIXED-POINT UNIT
The fixed-point unit implements all fixed-point processor instructions, except the fixed-point
storage access instructions that are implemented by the load/store unit. Refer to the
PowerPC Microprocessor Family: The Programming Environment for 32-Bit
Microprocessors
manual for more information.
6.5.1 XER Update In Divide Instructions
The divide instructions have a relatively long latency, but those instructions can update the
OV bit in the XER after one cycle. Therefore, data dependency on the XER is limited to one
cycle, although the divide instruction latency can be a maximum of 11 clocks.
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