Instruction Cache
MOTOROLA MPC823e REFERENCE MANUAL 9-15
INSTRUCTION CACHE
9
9.9 DEBUG SUPPORT
The MPC823e can be debugged either in debug mode or by a software monitor debugger.
In both cases, the core of the MPC823e CPU asserts the internal freeze (FRZ) signal. When
FRZ is asserted the instruction cache treats all misses as if they were from cache-inhibited
regions and, assuming the debug routine is not in the instruction cache, the cache state
remains exactly the same. When FRZ is asserted, hits are still read from the array and the
LRU bits are updated. Therefore, in the simple case of the debug routine it is read from
memory like any other miss. However, for performance reasons, it might be preferable to
run the debug routine from the cache. Follow these steps with little variation:
1. Save all four ways of the sets that are needed for the debug routine by reading the tag,
LRU code bit, valid bit, and lock bit values.
2. Unlock the locked ways in the selected sets.
3. Use a LOAD & LOCK command to load and lock the debug routine into the instruction
cache (LOAD & LOCK operates the same when FRZ is asserted).
4. Run the debug routine. All accesses to it will result in hits.
After the debug routine has completed, the old state of the instruction cache can be restored
by following these steps:
1. Unlock and invalidate all the sets that are used by the debug routine (both ways).
2. Use a LOAD & LOCK command to restore the old sets.
3. Unlock the ways that were not previously locked.
4. To restore the old state of the LRU, accesses must be made in the second LRU way,
the third LRU way and the MRU way. An access in this description is either LOAD &
LOCK or UNLOCK LINE.
9.9.1 Fetching Instructions From The Development Port
When the MPC823e is in debug mode, all instructions are fetched from the development
port, regardless of the address generated by the MPC823e core. Therefore, the instruction
cache is practically bypassed when the MPC823e is in debug mode.
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