MOTOROLA
MPC823e REFERENCE MANUAL
6-1
CORE
6
SECTION 6
THE P
OWER
PC CORE
The MPC823e core is where the PowerPC
â„¢
architecture is implemented. It has the
functionality of the PowerPC branch processor and fixed-point processor and includes all
the PowerPC user mode (problem mode) instructions, except floating-point instructions,
relevant privileged instructions, and all the registers associated with the processors and
instructions. In addition, it contains part of the development support features of the
MPC823e, including breakpoint and watchpoint support, program flow tracking data
generation, and debug mode operation in which the core is controlled by the development
support system through the debug port module.
This section describes the functional specifications of the core. It is based on a document
called the
PowerPC Microprocessor Family: The Programming Environment for 32-Bit
Microprocessors
(MPCFPE32B/AD). Any reference to 64-bit implementation is not
supported by this core. Only a subset of the PowerPC architecture books are supported, as
indicated in
Appendix B MPC823e Instruction Set
.
6.1 FEATURES
The following is a list of the core’s main features:
• 32-bit PowerPC Architecture
• Single-Issue Integer Machine
• Variable Pipeline Depth Architecture Tailored to Instruction Complexity
• Fully Static Design
• Out-of-Order Execution Termination
• Branch Prediction for Prefetch
• 32
×
32-Bit General-Purpose Register File
• Precise Exception Model
• Extensive Debug/Testing Support
To Next Page
Loading...
Need help?
General
