Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-455
SPI
COMMUNICATION
16
PROCESSOR MODULE
9. Write 0xFF to the SPIE register to clear any previous events.
10.Write 0x37 to the SPIM register to enable all possible serial peripheral interface
interrupts.
11.Write 0x00000020 to the CIMR to allow the serial peripheral interface to generate a
system interrupt. The CICR must also be initialized.
12.Write 0x0170 to the SPMODE register to enable normal operation (not loopback),
master mode, and 8-bit characters. The SPI baud rate generator speed is ignored
because the serial peripheral interface is in slave mode.
13.Set the STR bit in the SPCOM register to enable the serial peripheral interface to be
ready once the master begins the transfer.
16.12.7 Handling Interrupts in the SPI
The following sequence must be followed to handle interrupts in the serial peripheral
interface.
1. Once an interrupt occurs, read the SPIE register to discover the cause of the
interrupts. Normally, the SPIE bits must be cleared at this time.
2. Process the TX buffer descriptor to reuse it and the RX buffer descriptor to extract the
data from it. To transmit another buffer, simply set the R bit of the TX buffer descriptor,
the E bit of the RX buffer descriptor, and the STR bit of the SPCOM register.
3. Clear the SPI bit in the CISR.
4. Execute the rfi instruction.
Note: If the master transmits 3 bytes and negates the SPISEL pin, the RX buffer
descriptor is closed, but the TX buffer descriptor remains open. If the master
transmits 5 or more bytes, the TX buffer descriptor is closed after the fifth byte.
If the master transmits 16 bytes and negates the SPISEL
pin, the RX buffer
descriptor is closed with no errors and no out-of-buffer error occurs. If the master
transmits more than 16 bytes, the RX buffer descriptor is closed (completely full)
and the out-of-buffer error occurs after the 17th byte is received.
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