Introduction
MOTOROLA MPC823e REFERENCE MANUAL 1-9
INTRODUCTION
1
The DRAM interface supports 8-, 16-, and 32-bit ports and uses a programmable state
machine to support almost any memory interface. Memory banks can be defined in depths
of 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, or 64M for all port sizes. In addition, the memory
depth can be defined as 64K and 128K for 8-bit memory or 128M and 256M for 32-bit
memory. The DRAM controller supports page mode access for successive transfers within
bursts. Although the MPC823e supports a glueless interface to DRAM, the capacitance of
the system bus may require that there be external buffers. The refresh unit provides CAS
before RAS
, a programmable refresh timer, refresh active during external reset, disable
refresh modes, and stacking for a maximum of seven refresh cycles.
1.2.3 The Communication Processor Module
The communication processor module (CPM) contains features that allow the MPC823e
microprocessor to excel in imaging, personal communication, and low-power applications.
These features are divided into three categories:
• DSP processing
• Communication processing
• Twelve serial DMA channels and two independent DMA channels
The MPC823e’s embedded DSP function allows the communication processor module to
execute imaging algorithms in parallel with the PowerPC core to achieve maximum
performance with very little power. The DSP can execute one 16x16 MAC on every clock
cycle. It has preprogrammed filtering functions like FIR, MOD, DEMOD, IIR, and
downloadable imaging functions for JPEG image compression and decompression. These
functions are also used by modem and speech recognition programs.
The robust communication features of the MPC823e are provided by the communication
processor module. These features include a RISC microcontroller with multiply accumulate
(MAC) hardware, two serial communication controllers (SCCs), two serial management
controllers (SMCs), one dedicated serial channel for the universal serial bus (USB), one
inter-integrated circuit (I
2
C) port, one serial peripheral interface (SPI), 8K dual-port RAM, an
interrupt controller, a time-slot assigner, and four independent baud rate generators.
Twenty serial DMA channels support the SCCs, SMCs, USB channel, SPI, and I
2
C
controllers. The independent DMAs give you two channels for general-purpose DMA usage.
They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent
request and acknowledge logic. The RISC microcontroller is the only block that can access
the IDMA registers directly. The CPU can only access them indirectly via a buffer descriptor.
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