Data Cache
MOTOROLA
MPC823e REFERENCE MANUAL
10-3
DATA CACHE
10
10.3 PROGRAMMING THE DATA CACHE
10.3.1 PowerPC Architecture Instructions
The following PowerPC instructions are supported by the data cache.
10.3.1.1 P
OWER
PC USER INSTRUCTION SET ARCHITECTURE (BOOK I)
The data cache supports the
sync
instruction through a cache pipe clean indication to the
core.
Figure 10-2. Cache Data Path Block Diagram
4
WORDS
DIRTY
BUFFER
DATA
INTERNAL
8K
SET
ADDRESS [20:27]
4
CACHE
ARRAY
DECODER
128
32
WORDS
BURST
BUFFER
32
128
STREAM
HIT
MUX
2->1
WORD
SELECT
MUX
4->1
32
DATA
BYPASS
MUX
2->1
32
32
TO CORE
BUS DATA