External Bus Interface
13-12
MPC823e REFERENCE MANUAL
MOTOROLA
EXTERNAL BUS
13
INTERFACE
13.4.2.2 SINGLE BEAT WRITE FLOW.
The basic write cycle begins with a bus arbitration,
followed by the address transfer and the data transfer. The handshakes are illustrated in
Figure 13-6, Figure 13-7, Figure 13-8, and Figure 13-9 as applicable to the fixed transaction
protocol.
Figure 13-6. Basic Flow Diagram of a Single Beat Write Cycle
MASTER SLAVE
REQUEST BUS (BR
)
RECEIVES BUS GRANT (BG
) FROM ARBITER
ASSERTS BUS BUSY (BB
) IF NO OTHER MASTER IS DRIVING
ASSERT TRANSFER START (TS
)
DRIVES ADDRESS AND ATTRIBUTES
DRIVES DATA
ASSERTS TRANSFER ACKNOWLEDGE (TA
)
STOPS DRIVING DATA
RECEIVES ADDRESS
RECEIVES DATA