Motorola MPC823e User Manual

PowerPC Architecture Compliance
7-8 MPC823e REFERENCE MANUAL MOTOROLA
PPC ARCHITECTURE
7
COMPLIANCE
7.3.7.2 PROCESSING. In each interrupt handler, when registers SRR0 and SSR1 are
saved, MSR
RI
can be set to 1.
7.3.7.3 DEFINITIONS. The following table defines the offset value by interrupt type and the
sections that follow describe each interrupt in detail.
Table 7-1. Offset of First Instruction by Interrupt Type
OFFSET (HEX) INTERRUPT TYPE
00000 Reserved
00100 System Reset
00200 Machine Check
00300 Data Storage
00400 Instruction Storage
00500 External
00600 Alignment
00700 Program
00800 Floating Point Unavailable
00900 Decrementer
00A00 Reserved
00B00 Reserved
00C00 System Call
00D00 Trace
00E00 Floating Point Assist
01000 Implementation-Dependent Software Emulation
01100 Implementation-Dependent Instruction TLB Miss
01200 Implementation-Dependent Data TLB Miss
01300 Implementation-Dependent Instruction TLB Error
01400 Implementation-Dependent Data TLB Error
01500 - 01BFF Reserved
01C00 Implementation-Dependent Data Breakpoint
01D00 Implementation-Dependent Instruction Breakpoint
01E00 Implementation-Dependent Peripheral Breakpoint
01F00 Implementation-Dependent Nonmaskable Development Port

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English