The PowerPC Core
MOTOROLA
MPC823e REFERENCE MANUAL
6-5
CORE
6
6.3.1 Flow Control
Flow control operations, or branches disrupt normal instruction pipeline flow. A change in
program flow creates bubbles in the pipeline because of the time it takes to fetch the newly
targeted instruction stream. In typical code, with 4 or 5 sequential instructions between
branches, the machine could waste up to 25% of its execution bandwidth waiting on branch
latency.
The sequencer maintains a 4-instruction deep instruction prefetch queue to execute
branches in parallel with the execution of sequential instructions. Ideally, a sequential
instruction is issued every clock, even when branches are present in the code. This is
referred to as branch folding. The instruction prefetch queue also eliminates stalls due to
long latency instruction fetches and all instructions are fetched into the instruction prefetch
queue, but only sequential instructions are issued to the execution units when they reach
the head of the queue. Branches enter the queue to mark watchpoints. See
Section 20
Development Capabilities and Interface
for details. Since branches do not prevent the
issue of sequential instructions unless they come in pairs, the performance impact of
entering branches in the instruction prefetch queue is negligible.
Figure 6-4. Sequencer Data Path
INSTRUCTION ADDRESS GENERATOR
CC UNIT
32
INSTRUCTION BUFFER
32
INSTRUCTION
PREFETCH
QUEUE (4)
32
BRANCH
CONDITION
EVALUATION
EXECUTION UNITS AND REGISTERS FILES
INSTRUCTION MEMORY SYSTEM
READ / WRITE
BUSSES
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