Data Cache
10-14 MPC823e REFERENCE MANUAL MOTOROLA
DATA CACHE
10
10.5.4 Data Cache Instructions
10.5.4.1 dcbi, dcbst, dcbf AND dcbz INSTRUCTIONS
The dcbz, dcbi, dcbst, and dcbf instructions operate on a block basis of cache line, which
is 16 bytes (4 words) long. A data TLB miss exception is generated if the effective address
of one of these instructions cannot be translated and data address relocation is enabled.
10.5.4.2 TOUCH. The dcbt and dcbtst instructions of the MPC823e operate on a block
basis of cache line, which is 16 bytes (4 words) long. Touch instructions initiate bus transfers
to bring in a cache line of data from memory. They become no operation instructions if the
effective address cannot be translated when the memory management unit is enabled.
10.5.4.3 STORAGE SYNCHRONIZATION/RESERVATION. The lwarx and stwcx.
instructions are implemented according to the PowerPC architecture requirements. When
the storage accessed by the lwarx and stwcx. instructions is in the Cache Allowed mode,
it is assumed that the system works with the single master in this storage region. Therefore
in the case of a data cache miss, the access on the internal and external buses do not have
a reservation attribute.
The MPC823e does not cause the system data storage error handler to be invoked if the
storage accessed by the lwarx and stwcx. instructions is in the Write Through Required
mode. The MPC823e does not provide support for snooping an external bus activity outside
the chip. The provision is made to cancel the reservation inside the MPC823e by using the
CR_B and KR_B input pins. The data cache has a snoop logic to monitor the internal bus
for CPM accesses of the address associated with the last lwarx instruction.
10.5.5 Data Cache Read
To allow debug and recovery actions, the MPC823e allows you to read the content of the
tags array as well as the last copyback address and data buffers. See
Section 10.3.3 Special Registers of the Data Cache for details. This operation is
privileged and any attempt to perform it when the core is in the problem state (MSR
PR
=1)
results in a program interrupt.
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