Motorola MPC823e User Manual

PowerPC Architecture Compliance
MOTOROLA MPC823e REFERENCE MANUAL 7-11
PPC ARCHITECTURE
7
COMPLIANCE
7.3.7.3.6 Program Interrupt. The MPC823e cannot generate a floating-point exception
type interrupt. Likewise, an illegal instruction type program interrupt is not generated by the
core, but an implementation-dependent software emulation interrupt is generated instead.
A privileged instruction program interrupt is generated for an on-core valid special-purpose
register (SPR) field or any SPR encoded as an external special register if SPR
0
=1 and
MSR
PR
=1, as well as if you try to execute privileged instruction occurred when MSR
PR
=1.
See Table 6-11 for details.
7.3.7.3.7 Floating-Point Unavailable Interrupt. The MPC823e cannot generate a
floating-point exception type interrupt. An implementation-dependent software emulation
interrupt will be taken when you try to execute floating-point instruction, regardless of
MSR
FP
.
7.3.7.3.8 Trace Interrupt. A trace interrupt occurs if MSR
SE
= 1 and any instruction except
rfi is successfully completed or if MSR
BE
= 1 and a branch is completed. Notice that the trace
interrupt does not occur after an instruction that causes an interrupt. The monitor/debugger
software must change the vectors of other possible interrupt addresses to single-step these
instructions. If this is unacceptable, other debug features can be used. Refer to
Section 20 Development Capabilities and Interface for more information. The following
registers are set on a trace interrupt:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction following the executed instruction.
SRR1—Save/Restore Register 1
1–4 Set to 0.
10–15 Set to 0.
Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
MSR—Machine State Register
IP No change.
ME No change.
LE Bits are copied from the ILE.
Other Set to 0.
Execution resumes at offset x’00D00’ from the base address indicated by MSR
IP
.
7.3.7.3.9 Floating-Point Assist Interrupt. The floating-point assist interrupt is not
generated by the MPC823e. An implementation-dependent software emulation interrupt will
be taken when you try to execute a floating-point instruction.

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English