PowerPC Architecture Compliance
7-4
MPC823e REFERENCE MANUAL
MOTOROLA
PPC ARCHITECTURE
7
COMPLIANCE
7.1.9.4 STORAGE SYNCHRONIZATION INSTRUCTIONS.
For these type of instructions,
EA must be a multiple of four. If it is not, the system alignment error handler is invoked.
7.1.9.5 OPTIONAL INSTRUCTIONS.
No optional instructions are supported.
7.1.9.6 LITTLE-ENDIAN BYTE ORDERING.
The load/store unit supports little-endian byte
ordering as specified in the
PowerPC User Instruction Set Architecture (Book I)
. In
little-endian mode, if an attempt is made to execute an individual scalar unaligned transfer,
as well as a multiple or string instruction, an alignment interrupt is taken.
7.2 P
OWER
PC VIRTUAL ENVIRONMENT ARCHITECTURE (BOOK II)
7.2.1 Storage Model
The MPC823e caches are structured as follows:
• Physically addressed split 2K instruction cache and 1K data cache
• Two-way set associative managed with LRU replacement algorithm
• 16-byte (4 words) line size with one valid bit per line
7.2.1.1 MEMORY COHERENCE.
Hardware memory coherence is not supported in the
MPC823e hardware, but can be performed in the software or by defining storage as cache
inhibited. In addition, the MPC823e does not provide any data storage attributes to an
external system.
7.2.1.2 ATOMIC UPDATE PRIMITIVES.
Both the
lwarx
and
stwcx
instructions are
implemented according to the PowerPC architecture requirements. When the storage
accessed by the
lwarx
and
stwcx
instructions is in the cache-allowed mode, it is assumed
that the system works with the single master in this storage region. Therefore, if a data
cache miss occurs, the access on the internal and external buses does not have a
reservation attribute.
The MPC823e does not cause the system data storage error handler to be invoked if the
storage accessed by the
lwarx
and
stwcx
instructions is in the writethrough required mode.
Also, the MPC823e does not provide support for snooping an external bus activity outside
the chip. The provision is made to cancel the reservation inside the MPC823e by using the
CR_B and KR_B input pins. Data cache has a snoop logic to monitor the internal bus for
communication processor module accesses of the address associated with the last
lwarx
instruction.
To Next Page
Loading...
Need help?
General
