The PowerPC Core
MOTOROLA
MPC823e REFERENCE MANUAL
6-11
CORE
6
6.3.5 Processing an Interrupt
The following table provides the significant events that occur when processing an interrupt.
Table 6-3. Special Ports to Machine State Register Bits
MNEMONIC SPR MSR
EE
MSR
RI
USED FOR
EIE 80 1 1 External Interrupt Enable:
End of Interrupt Handler’s Prologue, Enable Nested
External Interrupts;
End of Critical Code Segment in Which External
Interrupts
Were Disabled
EID 81 0 1 External Interrupt Disable, But Other Interrupts Are Recoverable:
End of Interrupt Handler’s Prologue, Keep External
Nested Interrupts Disabled;
Start of Critical Code Segment in Which External
Interrupts Are Disabled
NRI 82 0 0 Nonrecoverable Interrupt:
Start of Interrupt Handler’s Epilogue
Table 6-4. Interrupt Latency
TIME POINT FETCH ISSUE INSTRUCTION COMPLETE KILL PIPELINE
A Faulting Instruction
Issue
B Instruction Complete
and All Previous
Instructions Complete
C Start Fetch
Handler
Kill Pipeline
D
≤
B + 3 Clocks
E First Instruction of
Handler Issued
NOTES:
1. At time point A an instruction that will cause an interrupt is issued.
2. At time point B the excepting instruction has reached the head of the history queue, thus implying that
all instructions preceding it in the code stream have finished execution without generating any interrupt.
Also, the excepting instruction itself has completed execution. At this time the exception is “recognized”
and exception processing begins. If, at this point, the instruction had not generated an exception, it
would have been retired.
3. At time point C the sequencer starts to fetch the interrupt handler’s first instruction.
4. By time point D the state of the machine prior to the issue of the excepting instruction is restored (the
machine is restored to its state at time.
5. At time point E the machine state register and instruction pointer of the executing process have been
saved and control has been transferred to the interrupt handler routine.
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