MOTOROLA
MPC823e REFERENCE MANUAL
11-1
MEMORY MANAGEMENT
11
UNIT
SECTION 11
MEMORY MANAGEMENT UNIT
The MPC823e implements a virtual memory management scheme that provides cache
control, storage access protection, and effective-to-real address translation. This
implementation includes separate instruction and data memory management units. The
MPC823e memory management unit is compliant with the
PowerPC Microprocessor
Family: The Programming Environment for 32-Bit Microprocessors
manual
in relation to the
supported attributes, except that two new modes of operation have been added:
• PowerPC
â„¢
mode with extended encoding
• Domain manager mode
Available protection granularity sizes are page (4K, 16K, 512K, or 8M) or 1K subpage
(1K subpage resolution is supported for 4K pages only). The prefix Mx_ that appears before
a memory management unit control register name corresponds to instruction and data
cache conditions.
11.1 FEATURES
The following is a list of the memory management unit’s main features:
• 32-Entry Fully Associative Data and Instruction Translation Lookaside Buffers (TLBs)
• Multiple Page Size Support
• High Performance
• Supports Maximum of 16 Virtual Address Spaces
• Supports 16 Access Protection Groups
• Each Entry can be Programmed to Match Problem Accesses, Privileged Accesses, or
Both
• PowerPC MSR
IR
and MSR
DR
Controls Memory Management Unit Translation and
Protection
• Supports PowerPC
tlbie
and
tlbia
Instructions. No
tlbsync
Instruction is Supported,
but it is Implemented as a NOP Instruction.
• PowerPC
mtspr/mfspr
Instructions to and from the Implementation-Specific
Special-Purpose Registers can be Used for Programming
• A Scratch Register is Available for Software Tablewalks
• Designed for Minimum Power Consumption
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