MOTOROLA
MPC823e REFERENCE MANUAL
12-1
SYSTEM INTERFACE UNIT
12
SECTION 12
SYSTEM INTERFACE UNIT
The system interface unit controls system startup, initialization, operation, and protection,
as well as the external system bus. The system configuration and protection function
controls the overall system and provides various monitors and timers, including the bus
monitor, software watchdog timer, periodic interrupt timer, PowerPC
â„¢
decrementer,
timebase, and real-time clock. The clock synthesizer generates the clock signals for other
modules and external devices that the system interface unit uses. This circuitry generates
the system clock from an inexpensive 32kHz crystal or an oscillator with a maximum
frequency of 5MHz. The system interface unit supports various low-power modes that
supply different ranges of power consumption, functionality, and wake-up time. The clock
scheme supports low-power modes for applications that use baud rate generators and/or
serial ports in standby mode. The main system clock can be changed dynamically, but the
baud rate generators and serial ports work with a fixed frequency. For more information on
clocks, refer to
Section 5 Clocks and Power Control
.
The external bus interface handles the transfer of information between internal buses and
the memory or peripherals in the external address space. The MPC823e is designed to
allow external bus masters to request and obtain mastership of the system bus. For
additional information on bus operation, see
Section 13 External Bus Interface
. The
memory controller module provides a glueless interface to many types of memory devices
and peripherals and it supports a maximum of eight memory banks, each with their own
device and timing attributes. Memory control services are provided to both internal and
external masters. The MPC823e supports circuitboard test strategies through a
user-accessible test logic that is fully compliant with information in
Section 21 IEEE 1149.1 Test Access Port
.
Note:
The MPC823e’s external address bus is 26 bits wide, while the internal address
bus is 32 bits wide. Therefore, external accesses are considered internally as
26-bit accesses (A[6:31]) with A[0:5] equal to 0, while internal accesses are full
32-bit accesses.
To Next Page
Loading...
Need help?
General
