The PowerPC Core
MOTOROLA MPC823e REFERENCE MANUAL 6-31
CORE
6
6.6.12 Storage Control Instructions
Cache management instructions and lookaside buffer management instructions are
implemented by the load/store unit. These instructions are implemented as the special bus
write cycles, which are issued to the data cache interface.
6.6.13 Exceptions
6.6.13.1 DAR, DSISR, AND BAR OPERATION. The load/store unit keeps track of all
instructions and bus cycles. When a bus error occurs, the data address register (DAR) is
loaded with the cycle’s effective address. For a multicycle instruction, the effective address
of the first offending cycle is loaded.
The data storage interrupt status register (DSISR) notifies the error when an exception
caused by the load/store occurs. For a memory management unit error, this register is
loaded with the error status delivered by the memory management unit. For other
exceptions, the DSISR is loaded with the instruction information as defined by the PowerPC
architecture for alignment exception. The breakpoint address register (BAR) notifies the
address on which an L-bus breakpoint occurred. For a multicycle instruction, the BAR
contains the address of the first cycle with which the breakpoint condition was associated.
The BAR has a valid value only when a data breakpoint interrupt is taken. At any other time,
its value is boundedly undefined. The following situations cause the DAR, BAR, and DSISR
registers to be updated.
Table 6-13. Value Summary of the DAR, BAR, and DSISR Registers
INTERRUPT TYPE DAR VALUE DSISR VALUE BAR VALUE
Data Storage Interrupt Cycle EA Memory Management
Unit Error Status
Undefined
Alignment Interrupt Data EA Instruction Information Undefined
L-Bus Breakpoint Interrupt Does Not Change Does Not Change Cycle EA
Machine Check Interrupt Cycle EA Instruction Information Undefined
Implementation Dependent Software Emulation
Interrupt
Does Not Change Does Not Change Undefined
Floating-Point Unavailable Interrupt Does Not Change Does Not Change Undefined
Program Interrupt Does Not Change Does Not Change Does Not Change
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