Honeywell HPM User Manual

4 Fault Isolation
4.9 HPMM Alphanumeric Display
368 HPM High-Performance Process Manager Service R688
Honeywell December 2020
HPMM RAM Retention Startup Sequence
An HPMM RAM Retention startup is performed whenever power is restored and the CMOS memory
battery backup was successful in maintaining the integrity of the operating personality software and
database in the RAM memory.
When an HPMM RAM Retention Startup process is performed, only the Communications processor is
initially released from reset and executes from the Startup and Base Utility firmware. Once a RAM
Retention Startup is considered possible, program execute control is transferred to the previously loaded
Communications processor software image. The Control processor and I/O Link processors are then
released so that they can verify their respective Startup conditions. The following table lists a HPMM
RAM Retention startup to Run state.
ATTENTION
Due to security authentication in the EUCN network, at least one ENIM must
be up and running in order for an EHPM node to be able to perform a RAM
Retention startup. The EHPM is re-authenticated during a RAM retention
restart, and the ENIM is the master authenticator node.
ATTENTION
Due to the processor restart time of the EHPM, the RAM Retention response
time for the EHPM is slightly longer than that of a HPM.
Table 74 RAM Retention Startup Display Sequence
Detailed
Display
Non-Detailed
Display
Description
OK39
OK39
In the Run state (UCN node 39). This display does
not blink.
STRT
STRT
Communications processor based tests
T 0D
STRT
Global DRAM EDAC sweep
T 13
STRT
Global DRAM initialization
T 17
STRT
Communications processor Local RAM destructive
pattern test
T 1B
STRT
Communications processor Local RAM
initialization
T 21
STRT
UCN TBC Private RAM destructive pattern test
T 25
STRT
UCN TBC Private RAM initialization
T 3E
STRT
Communications processor builds memory
reference table.
T 59
STRT
Transition to the SW Alive state.
T 5E
STRT
Monitor Control processor local state change (i.e
release Control processor from reset state)
T 70
STRT
Control processor Local RAM destructive pattern
test
T 76
STRT
Control processor Local RAM initialization

Honeywell HPM Specifications

General

Brand	Honeywell
Model	HPM
Category	Network Hardware
Language	English

Summary

2. EQUIPMENT DESCRIPTION

2.3 HPM Subsystem Overview

Provides an overview of the HPM subsystem, including major assemblies and card file types.

2.4 HPMM and IOP Card Files

Discusses differences between HPMM and IOP card files, including models and conversion kits.

2.5 HPMM Card Files

Details HPMM card file configurations, functionality, card types, indicators, and diagnostic displays.

2.6 EHPM Card Files

Describes EHPM card file configurations, functionality, card types, indicators, and diagnostic displays.

2.7 Service failed EHPM cards flashed with Experion-integrated firmware

Provides procedures for servicing failed EHPM cards flashed with Experion-integrated firmware.

2.12 I/O Link Extender (Fiber Optic Link)

Describes I/O Link Extender features, guidelines, front panel indicators, and status indicators.

2.15 Power Systems

Discusses Power System features, types, 48-volt battery backup time, and CMOS backup time.

2.20 24 Vdc Fuse Protection

Details 24 Vdc fuse protection for card files, including fuse removal and insertion.

2.21 5 Vdc Fuse Protection

Covers 5 Vdc fuse protection for High-Performance I/O Link cards and HPMM components.

2.23 I/O Link Interface Cabling

Covers I/O Link interface cabling, including cable length, redundant cables, and shield grounding.

2.26 UCN Cable System

Explains the Universal Control Network (UCN) cable system, including components and cable taps.

2.27 EUCN Cable System

Covers the Enhanced Universal Control Network (EUCN) cable system, including FTE cables and fault diagnosis.

2.28 UCN Node Address Pinning

2.29 I/O Link Interface Address Pinning

3. UCN Status Displays

3.5 HPM Status Displays

3.6 NIM Detail Status Displays

3.7 HPMM Detail Status Displays

3.8 IOP Detail Status Displays

4. FAULT ISOLATION

4.2 Failure Types

Defines Hard failures and Soft failures and their impact on HPM and IOP components.

4.3 Fault Isolation Concepts

4.6 Redundant Analog Output IOP Failure Diagnosis

Provides a procedure for diagnosing failures in redundant Analog Output IOPs.

4.9 HPMM Alphanumeric Display

5. UCN EXERCISER

6. REMOVAL AND REPLACEMENT

6.2 ESD Guidelines for HPMM and IOP Cards

Provides ESD prevention rules and guidelines for handling HPMM and IOP cards.

6.3 HPMM and IOP Cards

Details removal and replacement procedures for HPMM and IOP cards, including interface modules.

6.5 AO Standby Manual Device Operation

6.6 DO Standby Manual Device Operation

6.8 IOP to FTA Cable Replacement

6.9 FTA Module and Relay Replacement

6.13 48 V Backup Battery Replacement

6.14 Power Supply Module Replacement

6.17 I/O Link Extender Optical Coupler Module Replacement

7. IOP CALIBRATION PROCEDURES

7.2 LLAI, HLAI, and AO IOP Calibration

Covers common calibration procedures for LLAI, AO, and HLAI subsystems, including IOP/FTA substitution.

7.4 LLAI IOP Calibration Procedure

Details LLAI IOP calibration, including ranges, slot effects, range selection, and RTD/TC calibration.

7.5 Nonredundant HLAI IOP Calibration Procedure

Provides calibration procedures for nonredundant HLAI FTAs, including connection points and terminals.

7.6 Redundant HLAI IOP Calibration Procedure

Details simultaneous IOP calibration for redundant HLAI IOPs, including connections.

7.7 Nonredundant AO IOP Calibration Procedure

Provides calibration procedures for nonredundant AO IOPs, including isolation and calibration targets.

7.8 Redundant AO IOP Calibration Procedure

Details simultaneous IOP calibration for redundant AO IOPs, requiring specific FTA connections.

7.9 LLMux IOP Calibration Procedure

7.10 RHMUX IOP Calibration Procedure

8. PERIODIC REDUNDANCY TESTS

8.2 HPMM Redundancy

Discusses HPMM redundancy and how to confirm swap positions using display commands.

8.3 IOP Redundancy

Explains IOP redundancy terminology and provides a test procedure for redundant IOP configurations.

8.4 Redundant 8-Channel Analog Output IOPs

Details redundancy for 8-channel Analog Output IOPs, including hardware identification and test procedures.

8.5 Power Cable Redundancy

Covers redundant power cables for card files and distribution assemblies, including testing procedures.

8.6 Power Supply Module Redundancy

Discusses Power System redundancy and the test procedure for power capability.

9. SPARE PARTS