Vaisala RVP900 User Manual

Chapter 6 ______________________________________________________ Processing Algorithms
VAISALA______________________________________________________________________ 185
6.1 IF Signal Processing
The starting point for all computations within the RVP900 are the
instantaneous IF-receiver samples p
n
and, the instantaneous burst-pulse or
COHO reference samples b
n
. These data are available at a very high
sampling rate (typically 36 MHz), which makes possible the digital
implementation of functions that are traditionally performed by discrete
components in an analog receiver. The RVP900 all-digital approach
replaces a great deal of analog hardware, avoids problems of aging and
maintenance, and makes it easy to tune-up the receiver and alter its
parameters.
This section describes these IF signal processing steps. Refer to Figure 13
on page 39 for a block diagram of the IF processing that is performed.
6.1.1 FIR (Matched) Filter
The RVP900 implements a digital version of the "matched" filter that is
found in the traditional analog radar receiver. The equivalent FIR filter is
designed using an interactive graphical procedure described in Section 5.4
Ps — Plot Burst Spectra and AFC on page 148. The filter length (number
of taps), center frequency, and bandwidth are all adjustable. The design
procedure computes two sets of filter coefficients and such that the
instantaneous quadrature samples at a given bin are:
where N is the length of the filter. The input samples pn are centered on the
range bin to which the (I, Q) pair is assigned. Note that some of the p
n
are
likely to overlap among adjacent bins, that is, the filter length may be
chosen to be greater than the bin spacing. Such an overlap introduces a
slight correlation between successive bins, but the longer length allows a
better filter to be designed.
The sums above for I and Q are computed on the RVP900/Rx board using
dedicated FIR chips (for revisions A and B) that can perform up to 576
million sums of products per second. The Rev C RVP900/Rx uses a more
flexible FPGA. The p
n
are represented as 16-bit signed integers, and the
and are represented as 10-bit (Rev.A/B) or 16-bit (Rev.C) signed
integers. A numerical optimization procedure is used to quantize the ideal
filter coefficients into their hardware values. The overall spectral purity of
f
n
i
f
n
q
If
i
n
p
n
, Qf
q
n
pn
N 0=
N 1–

=
N 0=
N 1–

=
f
i
n
f
q
n

Vaisala RVP900 Specifications

General

Brand	Vaisala
Model	RVP900
Category	Receiver
Language	English