Vaisala RVP900 User Manual

Chapter 3 _______________________________________________________ Hardware Installation
VAISALA_______________________________________________________________________ 69
For the IF receiver input, it is permissible (in fact, desirable) to
occasionally exceed the A/D input saturation level at the strongest targets.
The RVP900 employs a statistical linearization algorithm to derive correct
power levels from targets that are as much as 6 dB above saturation. The
actual IF signal level should be established by weak-signal and noise
considerations (see below), rather than by working backwards from the
saturation level.
3.2.7 IFDR Clock Subsystem
The RVP901 provides a flexible, fully programmable, low jitter clock
generator used in sampling the IF inputs and generating the IF outputs.
- Master Clock Source—Clock reference can be provided by a
20 MHz on-board oscillator. An external clock reference may also be
provided to the RVP901 through CLK-IN (J7).
- IF Clock Frequency—The sampling clock frequency is fully
programmable between 50 MHz to 100 MHz (see Section 3.2.8
Choice of A/D Sample Rate and Tx Synthesis Rate on page 69) with
microhertz (μHz) resolution. The clock frequency can be chosen
independently of the original reference clock frequency that produces
it; they do not have to be small integer multiples of each other.
- Clock Jitter—IF clock jitter is sub-picosecond allowing the system
to maximize the benefits of the 16-bit A/D convertors.
The master clock source is software-configurable between the on-board
20 MHz reference or an external source. The external clock option allows
the IFDR to be phase locked to a standard system reference; however, the
external clock is not a requirement. The internal reference oscillator is a
high-quality oscillator, but is not temperature compensated. The internal
20 MHz reference frequence stability is 20 ppm over extended temperature
range of -40°C to +85°C (-40°F to +176°F). Its jitter is sub–picosecond.
The IFDR sampling clock is derived from the master clock source, using a
novel architecture recommended by Analog Devices. The architecture
minimizes jitter, while allowing full flexibility in selecting sampling
frequencies between 50 MHz to 100 MHz. The output clock runs at the
same frequency as the sampling clock.
When the RVP900 is used in a klystron system, or in any type of
synchronous radar, the radar COHO is supplied to the IFDR, so that the
sampling clock can digitally lock to it. The COHO phase is measured at the
beginning of each transmitted pulse, and is used to lock the subsequent
(I,Q) data for that pulse. The COHO phase is measured relative to the IFDR
internal stable sampling clock, which is user selectable. The internal
sampling clock is not affected by the application of the COHO. A/D

Vaisala RVP900 Specifications

General

Brand	Vaisala
Model	RVP900
Category	Receiver
Language	English