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Vaisala RVP900 User Manual

Vaisala RVP900
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Chapter 3 _______________________________________________________ Hardware Installation
VAISALA_______________________________________________________________________ 71
expectations of a synchronous radar system in which clutter rejection
of 55 dB to 60 dB should be attainable.
The solution to either of the these concerns is to provide some means for
the IFDR internal sampling clock to be phase locked to the radar system.
If the RVP900 provides the radar triggers, then those triggers become
synchronous with the radar COHO. If the RVP900 receives an external
trigger, then its range bin clock is synchronous with that external trigger,
and there is no synchronization jitter in the range bins.
The IFDR has the option of locking its sampling clock to an external
system clock reference through the CLK-IN SMA input. This results in an
RVP900 that is fully synchronous with the existing radar timing.
3.2.8 Choice of A/D Sample Rate and Tx
Synthesis Rate
The internal system clock, which samples the IF input signals and
synthesizes the Tx output waveforms, can be configured to run at any
frequency between 50 MHz and 100 MHz. The setup questions in the Mc
menu (see Section 4.2.1 Mc — Top Level Configuration on page 104)
select the sampling clock frequency and whether the clock is derived from
a stable on-board crystal oscillator or from the external CLK-IN SMA
reference.
The sample clock frequency is a far-reaching parameter that affects many
components of the radar and signal processing system. The choice of
frequency is likely to be different for each radar facility, because it
represents a trade-off of the following considerations:
- A/D Quantization Noise and Dynamic Range—The inherent SNR
of the A/D converter chip is spread over a Nyquist band, whose width
is determined by the sampling frequency (see Section 3.2.10 IF
Bandwidth and Dynamic Range on page 71). As the sampling
frequency increases, the A/D quantization noise that is contained
within a given Rx bandwidth decreases, which means that the
RVP900 becomes "more quiet". The dynamic range varies linearly
with sampling frequency; therefore, the RVP900 has 3 dB greater
dynamic range at 100 MHz versus 50 MHz clock.
- Quantization of Trigger Timing and Range Bin Placement—
Triggers generated by the RVP900 are specified by their start time in
microseconds, width in microseconds, and polarity. Triggers are
always produce that are ±0.5 clocks of these ideal values. However, if
you want the triggers to be precisely aligned down to the exact clock
edge, the sample clock frequency should be chosen so that trigger
edges fall on integer multiples of the clock period. Similarly, the range

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Vaisala RVP900 Specifications

General IconGeneral
BrandVaisala
ModelRVP900
CategoryReceiver
LanguageEnglish