USER’S MANUAL__________________________________________________________________
20 __________________________________________________________________ M211322EN-D
Much of the proven, tested, and documented software from the
highly-successful RVP8 (written in C) is ported directly to the new
RVP900 architecture. This allows Vaisala to reduce time-to-market and
produce a high-quality, reliable system. The RVP900 provides new
capabilities for weather radar systems that, until now, were not available
outside of the research community.
2.2 Dual Frequency Receive Options
For example, the RVP900 IF Digital Receiver (IFDR) performs 38.4
billion multiply accumulate cycles per second, which is a fivefold increase
over the RVP8. Parallel Finite Impulse Response (FIR) filter processing
blocks have been created to allow simultaneous dual frequency receive
strategies to be deployed. With the advanced digitally synthesized
transmitter function, this allows for new processing techniques still in the
research realm for weather radar applications, such as alternating dual
frequency staggered PRTs and pulse compression with off-frequency short
pulses to fill in the near range data.
2.3 Open Hardware and Software Design
Compared to previous processors that were built around proprietary DSP
chips and PCI card technology, the RVP900 is implemented around a
single FPGA and acts as a networked device connected through a CAT5e
ethernet to the latest in PC server technology. Eliminating the dependency
of multiple PCI slots on the host computer allows continued access to latest
improvement in processor speed, bus bandwidth, and the availability of
low-cost compatible hardware and peripherals. The performance of an
entry level RVP900 PC (currently dual quad-core 2.33 GHz Intel Xeon
processors) is approximately five times faster than the fastest RVP8 ever
produced (with dual 3.0 GHz Pentium processors).
The RVP900 IFDR produces digital I and Q data. The digital I and Q data
is given to a PC server to perform the processing using pulse pairs, Fourier
2009 RVP900 First IF digital receiver as a networked device
to a signal processing PC running a Linux
operating system. The PC bus-less
architecture allows the fastest PCs to be used
in signal processing role creating more
real-time processing possibilities. The
RVP900 contains all the functionality of the
RVP8 PCI cards and IFD on a single printed
circuit board.
Year Model Units Sold Major Technical Milestones
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