11-12 Limit Testing Models 2500 and 2502 User’s Manual
If the handler requires a high-going pulse, the four digital output lines of the Model 2500
must initially be set low. The LO, LO, LO, LO clear pattern represents the no action condi-
tion for the handler. When one of those lines are pulled high by a defined pass or fail bit
pattern (i.e., LO, LO, LO, HI), the DUT will be placed in the bit assigned to that pulsed
line.
Category register component handler
When using this type of handler, the Model 2500 sends a bit pattern to three handler lines
when a pass or fail condition occurs. This bit pattern determines the bin assignment for the
DUT. With the pass/fail pattern on the output, line #4 is then pulsed. This end-of-test
(EOT) pulse latches the bit pattern into the register of the handler, which places the DUT
in the assigned bin. When interfacing to this type of handler, a maximum of eight compo-
nent handler bins are supported.
If the handler requires a high-going or low-going EOT pulse, program Model 2500 for
3-bit operation and appropriate EOT mode.
NOTE The EOT and 3-bit modes are configured from the CONFIG LIMIT MENU. See
“Configuring limit tests,” page 11-16.
Basic binning systems
Two basic binning systems are shown in Figure 11-7 and Figure 11-8. Both systems
require a handler to physically place the device packages in the appropriate bins. The han-
dler is controlled by the Model 2500 via the Digital I/O port.
Single-element device binning
Figure 11-7 shows a basic binning system for single-element devices. After all pro-
grammed testing on the DUT is completed, the appropriate digital output information is
sent to the component handler, which then places the DUT in the appropriate bin. The
component handler selects the next DUT, and the testing process is repeated.
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