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14-8 Status Structure Models 2500 and 2502 User’s Manual

Status byte register

The summary messages from the status registers and queues are used to set or clear the

appropriate bits (B0, B2, B3, B4, B5, and B7) of the status byte register. These summary

bits do not latch, and their states (0 or 1) are solely dependent on the summary messages

(0 or 1). For example, if the standard event register is read, its register will clear. As a

result, its summary message will reset to 0, which in turn will reset the ESB bit in the sta-

tus byte register.

The bits of the status byte register are described as follows:

• Bit B0, Measurement Summary Bit (MSB) — Set summary bit indicates that an

enabled measurement event has occurred.

• Bit B1 — Not used.

• Bit B2, Error Available (EAV) — Set summary bit indicates that an error or status

message is present in the Error Queue.

• Bit B3, Questionable Summary Bit (QSB) — Set summary bit indicates that an

enabled questionable event has occurred.

• Bit B4, Message Available (MAV) — Set summary bit indicates that a response mes-

sage is present in the Output Queue.

• Bit B5, Event Summary Bit (ESB) — Set summary bit indicates that an enabled stan-

dard event has occurred.

• Bit B6, Request Service (RQS)/Master Summary Status (MSS) — Set bit indicates

that an enabled summary bit of the Status Byte Register is set.

• Bit B7, Operation Summary (OSB) — Set summary bit indicates that an enabled

operation event has occurred.

Depending on how it is used, Bit B6 of the Status Byte Register is either the Request for

Service (RQS) bit or the Master Summary Status (MSS) bit:

• When using the serial poll sequence of the Model 2500 to obtain the status byte (a.k.a.

serial poll byte), B6 is the RQS bit. See “Serial polling and SRQ” for details on using

the serial poll sequence.

• When using the *STB? command (Table 14-3) to read the status byte, B6 is the MSS

bit.

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Keithley 2500 User Manual

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