Debug and Strapping
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 117
15.2 JTAG and Debug UART
The following figure shows the JTAG and UART debug connections.
Figure 15-1. JTAG and UART Debug Connections
Jetson AGX Xavier
SoC
JTAG_T
MS
J TAG_T DI
JTAG_
TCK
JTAG_TDO
JTAG_T RST_N
NVJ TA G_ SEL
NVDBG_SEL
100kΩ
For Debug Use
DEBUG
J TAG_T MS
J T A G_T DI
J T A G_T CK
J T A G_T DO
JTAG_TRST_N
NVJ TA G_ SE L
NVDBG_SEL
SY S_ RES ET_ N
UART3_TX_DEBUG
UART3_RX_DEBUG
100kΩ
Se e N o te 1
Optional JTAG
con ne ction s
0Ω
To PMIC
R T CK
TMS
TDI
TCK
TDO
TRST_N
RST
VDD_1V 8_DBG
100kΩ
UART3_TX
UART3_RX
AO
E58
B6 0
A60
D58
G61
H59
G60
H62
K60
L60
100kΩ
0Ω
0Ω
Notes:
1. NVJTAG_SEL and JTAG_TRST_N must be low for normal operation and pulled to 1.8V for
Boundary Scan Mode. NVDBG is left unconnected (pulled down on module) for normal
operation and pulled to 1.8V for alternate debug modes (debug over USB, etc.). for Boundary
Scan test mode, JTAG_TRST_N must be driven high in the proper sequence. See the
Xavier
Boundary Scan Requirements and Usage
document for details.
2. Check preferred JTAG debugger documentation for JTAG PU/PD recommendations.
The Jetson AGX Xavier Developer Kit carrier board reference design implements a USB to
UART bridge. A simpler option is shown in the following figure. The UART3_DEBUG interface is
shown routed to a 6-pin header through level shifters.
Figure 15-2. Simple Debug UART Header Connections
Jetson AGX Xavier
SoC
1
2
3
4
5
6
Level Shifter
VCCBVCCA
B1A1
B2A2
GNDDIR
Level Shifter
VCCAVCCB
A1B1
A2B2
DIRGND
10 0kΩ
VDD_3V3VDD_1V8
0.1uF
0.1uF
0.1uF
0.1uF
Serial Port
Header
UART 3_TX_DEBUG
UART 3_RX_DEBUG
UART3_TX
UART3_RX
AO
H62
K60
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