Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 125
Chapter 17. Unused Interface
Terminations
17.1 Unused MPIO Interfaces
The following Jetson AGX Xavier pins (and groups of pins) are Jetson AGX Xavier MPIO (Multi-
purpose Standard CMOS Pad) pins that support either special function IOs (SFIO) and/or GPIO
capabilities. Any unused pins or portions of pin groups listed in the following table that are not
used can be left unconnected.
Table 17-1. Unused MPIO Pins and Pin Groups
Module Pins / Pin Groups Module Pins / Pin Groups Module Pins / Pin Groups
I2Sx, AUD_MCLK, DSPKx, DMICx SLVSx GPIO_AO_RET
SDMMCx IQCx WDT_RESET_x
MIPI_TRC_x UFSx TOUCH_x
EQOSx PEx, PEX_CLKx EXTPERIPHx
QSPIx DP_AUXx IGPUx
Ux3_x GP_PWMx SATA_LED_ACTIVE
I2Cx CCLAx NV_THERMx
SPIx SCE_SAFE_STATE ISTCTRLx
CANx SOC_THERMx DCx
VGPx PMICINTR DGPU_x
17.2 Unused SFIO Interface Pins
See the “Unused SFIO (Special Function I/O) Interface Pins” section in the pin description
checklist attached to this design guide.
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