Nvidia Jetson AGX Xavier Series User Manual

USB, PCIe, and UFS
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 39
Pin # Module Pin Name SoC Signal Usage/Description Usage on NVIDIA
Carrier Board
Direction Pin Type
C31 NVHS0_SLVS_RX6_P NVHS0_RX6_P PCIe/SLVS 0 Receive Lane 6. PCIe x8
controller #5 or SLVS, lane 6.
A31 NVHS0_SLVS_RX7_N NVHS0_RX7_N PCIe/SLVS 0 Receive Lane 7. PCIe x8
controller #5 or SLVS, lane 7.
A30 NVHS0_SLVS_RX7_P NVHS0_RX7_P
H25 NVHS0_TX0_N NVHS0_TX0_N
PCIe Transmit Lane 0. PCIe x8 controller
#5, lane 0.
Output UPHY Diff Pair
H24 NVHS0_TX0_P NVHS0_TX0_P
K24 NVHS0_TX1_N NVHS0_TX1_N PCIe
Transmit Lane 1. PCIe x8 controller
#5, lane 1.
K25 NVHS0_TX1_P NVHS0_TX1_P
G26 NVHS0_TX2_N NVHS0_TX2_N
PCIe Transmit Lane 2. PCIe x8 controller
#5, lane 2.
G27 NVHS0_TX2_P NVHS0_TX2_P
J27 NVHS0_TX3_N NVHS0_TX3_N PCIe Transmit Lane 3.
PCIe x8 controller
#5, lane 3.
J26 NVHS0_TX3_P NVHS0_TX3_P
H29 NVHS0_TX4_N NVHS0_TX4_N
PCIe Transmit Lane 4. PCIe x8 controller
#5, lane 4.
H28 NVHS0_TX4_P NVHS0_TX4_P
K28 NVHS0_TX5_N NVHS0_TX5_N PCIe Transmit Lane 5. PCIe x8
controller
#5, lane 5.
K29
NVHS0_TX5_P
NVHS0_TX5_P
G30 NVHS0_TX6_N NVHS0_TX6_N
PCIe Transmit Lane 6. PCIe x8 controller
#5, lane 6.
G31
NVHS0_TX6_P
NVHS0_TX6_P
J31 NVHS0_TX7_N NVHS0_TX7_N
PCIe Transmit Lane 7. PCIe x8 controller
#5, lane 7.
J30 NVHS0_TX7_P NVHS0_TX7_P
Notes:
1. In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals.
Table 7-4. PCIe Clock and Control Pin Descriptions
Pin #
Module Pin
Name
SoC Signal Usage/Description
Usage on NVIDIA
Carrier Board
Direction Pin Type
E14 PEX_CLK0_N PEX_CLK0N PCIe 0 Reference Clock for controller #0. M.2 Key M Connector Output PCIe Diff Pair
E15 PEX_CLK0_P PEX_CLK0P
E11 PEX_L0_
CLKREQ_N
PEX_L0_
CLKREQ_N
PCIe 0 Clock Request for controller #0. Pulled
to 3.3V through 47kΩ resistor on-module.
Input
Open-Drain –
3.3V
D10 PEX_L0_RST_N PEX_L0_RST_N PCIe 0 Reset for controller #0. Pulled to 3.3V
through 4.7kΩ resistor on-module.
Output
F17 PEX_CLK1_N PEX_CLK1N PCIe 1 Reference Clock for controller #1. eSATA Bridge Output PCIe Diff Pair
F16 PEX_CLK1_P PEX_CLK1P
D9 PEX_L1_
CLKREQ_N
PEX_L1_
CLKREQ_N
PCIe 1 Clock Request for controller #1. Pulled
to 3.3V through 47kΩ resistor on-module.
Unused Input Open-Drain –
3.3V
B9 PEX_L1_RST_N PEX_L1_RST_N PCIe 1 Reset for controller #1. Pulled to 3.3V
through 4.7kΩ resistor on-module.
eSATA Bridge Output
F21 PEX_CLK3_N PEX_CLK3N PCIe 3 Reference Clock for controller #3. M.2 Key E Connector Output Diff pair
F20 PEX_CLK3_P PEX_CLK3P
J10
PEX_L3_
CLKREQ_N
PEX_L3_
CLKREQ_N
PCIe 3 Clock Request for controller #3. Pulled
to 3.3V through 47kΩ resistor on-module.
Input
Open-Drain –
3.3V
K9 PEX_L3_RST_N PEX_L3_RST_N PCIe 3 Reset for controller #3. Pulled to 3.3V
through 4.7kΩ resistor on-module.
Output
E22 PEX_CLK4_N PEX_CLK4N PCIe 4 Reference Clock for controller #4, Unused Output Diff pair
E23 PEX_CLK4_P PEX_CLK4P
G8 PEX_L4_
CLKREQ_N
PEX_L4_
CLKREQ_N
PCIe 4 Clock Request for controller #4. Pulled
to 3.3V through 47kΩ resistor on-module.
Input Open-Drain –
3.3V
J9 PEX_L4_RST_N PEX_L4_RST_N PCIe 4 Reset for controller #4. Pulled to 3.3V
through 4.7kΩ resistor on-module.
Output
F25 PEX_CLK5_N PEX_CLK5N
PCIe 5 Reference Clock for controller #5 when
Jetson AGX Xavier is Root Port. Unused when
Jetson AGX Xavier used as Endpoint.
PCIe x16 Connector Output Diff pair
F24 PEX_CLK5_P PEX_CLK5P
C8
PEX_L5_
CLKREQ_N
PEX_L5_
CLKREQ_N
PCIe 5 Clock Request for controller #5. Input
when Jetson AGX Xavier is Root Port. Output
Input
Open-Drain –
3.3V

Nvidia Jetson AGX Xavier Series Specifications

General

Brand	Nvidia
Model	Jetson AGX Xavier Series
Category	Computer Hardware
Language	English