Nvidia Jetson AGX Xavier Series User Manual

USB, PCIe, and UFS
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 49
Figure 7-5. PCIe Endpoint Connection Example
Jetson AGX Xavier
SoC - PCIe
PEX_WAKE_N
PEX
Control
VDDIO_AO_3V3
PEX_L5_CLKREQ_N
PEX_L5_RST_N
NVHS 0_SLV S_ RX0 _N /P
NVHS0_TX0_N/P
NVHS 0_SLV S_ RX1 _N /P
NVHS0_TX1_N/P
NVHS 0_SLV S_ RX2 _N /P
NVHS0_TX2_N/P
NVHS 0_SLV S_ RX3 _N /P
NVHS0_TX3_N/P
NVHS 0_SLV S_ RX4 _N /P
NVHS0_TX4_N/P
NVHS 0_SLV S_ RX5 _N /P
NVHS0_TX5_N/P
NVHS 0_SLV S_ RX6 _N /P
NVHS0_TX6_N/P
NVHS 0_SLV S_ RX7 _N /P
NVHS0_TX7_N/P
PEX_CLK5_N/P
NVHS0_SLVS_REFCLK_N/P
C8
H10
A8
PEX_CLK5_ N/P
F25/F24
PE X_ L5 _ CLK REQ _N
PEX_L5_RST_N
PE X_ WAKE_ N
PCIe x8 (I/F C5 )
Cont r ol f or PCIe I/ F C5
(PCIe x16 Connector on Carrier Board)
NVHS0_
RX0_N/P
NVHS0_TX0_N/P
NVHS0_
RX3_N/P
_
NVHS0_
TX3_N/P
NVHS0_
RX5_N/P
NVHS0_TX5_N/P
NVHS0_
RX4_N/P
NVHS0_TX4_N/P
NVHS0_
RX1_N/P
NVHS0_TX1_N/P
NVHS0_RX2_N/P
NVHS0_
TX2_N/P
NVHS0_RX6_N/P
NVHS0_TX6_N/P
NVHS0_RX7_N/P
NVHS0_TX7_N/P
0.22uF
H25/H24
D25/D24
0.22uF
K24/K25
B2 4/B25
0.22uF
G26/G27
C26/C27
0.22uF
J27/J26
A27/A26
0.22uF
H29/H28
D29/D28
0.22uF
K28/K29
B2 8/B29
0.22uF
G30/G31
C30/C31
0.22uF
J31/J30
A31/A30
NVHS
4.7kΩ
47kΩ
NVHS0_REFCLK_N/P
E31/E30
100MHz clock input required to support
Endpoint on PCIe x8 (NVHS pins – C5)
Not used when module C5
I/F is used as Endpoint
Not used by PCIe I/F configured as Endpoint.
Used for Root Port Wake only.
4.7kΩ
L ane 0
L ane 1
L ane 2
L ane 3
L ane 4
L ane 5
L ane 6
L ane 7
Note: See “Notes” under Figure 7-4.

Nvidia Jetson AGX Xavier Series Specifications

General

Brand	Nvidia
Model	Jetson AGX Xavier Series
Category	Computer Hardware
Language	English