Jetson AGX Xavier Series Product DG-09840-001_v2.5 | iv
Version Date Description of Change
• Updated with relaxed skews based on frequency
(0.4*UI)
I2C
• Updated figure module pin #s for I2C3
Boundary Scan
• Updated Boundary Scan figure module pin #s
Pin Descriptions
• Corrected I2S1 pin #s, description and direction.
2.0 May 12, 2020 Main 699-pin Connector Details
• Added Module Installation and Removal Section
Video Input
• Added SLVS XCE and SCLR signals to Pin Desc.
• Added pin tolerance were applicable
• Updated control signal direction to match SLVS usage
• Update SLVS connection figure:
• Corrected XCE and XCLR connections and changed to
generic name for SLVS imager/connector in figure
• Added SLVS connections tables
I2C and Design Checklist (I2C section)
• Added note for series resistors on I2C for M.2 sockets
2.1 July 27, 2020 • Update Table 2-1 to C5 only supports EP
• Added Chapter 4 on reference design considerations
• Added DV/Dt section (Section 5.5.1) including optional disable
or tuning
• Added optional additional diode to DV/dt circuit to allow more
drop before triggering system shutdown (asserting
VDDIN_PWR_BAD_N) in Figure 5-12
• Added descriptions per lane for data lane pin descriptions
table (Table 7-2)
• Added more details to the “Usage/Description” column in
Table 7-3
• Updated to reflect RP only and added details for EP usage to
the PCIe clock and control pin descriptions table (Table 7-4)
• Updated Section 7.2 “PCI Express” for C5 only as EP
• Updated Figure 7-4 for C5 only as EP
• Removed C0 and C4 as EP in Figure 7-5
• Added UPHY_REFCLK1/2_N/P pins but indicated it is unused
as EP not supported on C0 and C4 in Table 7-14
• Added NVHS0_SLVS_REFCLK_N/P pin to Table 7-14
• Removed C0 and C4 from Table 7-15 as these are no longer
supported as Eps
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