4.16 Sub Monitor
4-75
2. Change of the connecting ports
The output of slaves 1 and 2 can change to the Semi-log or the Full-log output.
Fig. 4.16.2 Video Signal System Diagram
Fig. 4.16.3 Location of JP3 to JP6 on the SPU Board
Factory setting Jumper
J3 J4 J5 J6
J617
(SLAVE 1)
Full
log
J618
(SLAVE 2)
Semi
log
Yes No No Yes
RF unit
IF + Video MIX
U46
SPU FPGA
RF Tx/Rx
BP
HD
TRIG
U30
U41
U40
OP HD OUT-1
HD IN
TRIG IN
BP IN
OP VIDEO OUT-1 (FULL LOG)
OP VIDEO OUT-2 (SEMI LOG)
SEMI LOG VIDEO
OP HD OUT-2
OP BP OUT-1
OP BP OUT-2
OP TRIG OUT-1
OP TRIG OUT-2
FULL LOG OUT
Log AMP
(Video sig.)
IF AMP
(Liner: 60MHz)
IF AMP
(60MHz)
IF input
IF AMP p.c.b
LPF
(L/C)
HPF
(L/C)
Long Pulse FIL
(BW: 2.5MHz)
MIdle Pulse FIL
(BW: 10MHz)
Short Pulse FIL
(BW: 35MHz)
DET
(U86)
U85
U78
U78
U87
JP3
JP4
JP5
JP6
BW A/B sel
TEST ECHO
SEL
(U83)
A/D
(U76)
U85
OP VIDEO IN
OP VIDEO IN
R401
SEL VIDEO
8bit
ARPA/MAIN CPU
Echo data
RPU-013
RFC p.c.b
SPU p.c.b
J616
Master Radar
J617, J618
SUB Display-1, 2
J617, J618
SUB Display-1, 2
MIX
AD/DATA
TP58
GAIN/STC CONT