10
FUNCTIONS AND PROGRAMMING
10.3 Programming Using MELSEC Data Link Functions
10.3.12 Accessible ranges and devices of MELSEC data link functions
10 - 50
9
UTILITY OPERATION
10
FUNCTIONS AND
PROGRAMMING
11
OVERVIEW OF
MULTIPLE CPU
SYSTEM
12
MULTIPLE CPU
SYSTEM
CONFIGURATION
13
MULTIPLE CPU
SYSTEM
CONCEPT
14
COMMUNICATIONS
BETWEEN CPU
MODULES
15
PARAMETERS
ADDED FOR
MULTIPLE CPU
16
PRECAUTIONS FOR
USE OF AnS SERIES
MODULE
: Accessible, : Inaccessible
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Table10.21 Accessible devices at the time of other station access(Continued)
Device
Device type
(Device name specification)
Access target
Programmable controller CPU
V (index register)
Batch
DevV
Random
R (file register)
Batch
DevR
Random
ER (extension file register)
Batch
DevER(0) to DevER(256)
Random
B
Batch
DevB
Random
W
Batch
DevW
Random
Q/QnA link special relay
(within the Q/QnACPU)
Batch
DevQSB
Random
Retentive timer (contact)
Batch
DevSTT
Random
Retentive timer (coil)
Batch
DevSTC
Random
Q/QnA link special register
(within the Q/QnACPU)
Batch
DevQSW
Random
Q/QnA link edge relay
(within the Q/QnACPU)
Batch
DevQV
Random
Own station random access buffer
Batch
DevMRB
Random
Retentive timer (current value)
Batch
DevSTN
Random
Own station link register
(for sending)
Batch
DevWw
Random
Own station link register
(for receiving)
Batch
DevWr
Random
Own station buffer memory
Batch
DevSPB
Random
Direct link input
(other station side)
Batch
DevLX(1) to DevLX(255)
Random
Direct link output
(other station side)
Batch
DevLY(1) to DevLY(255)
Random
Direct link relay
(other station side)
Batch
DevLB(1) to DevLB(255)
Random
Direct link register
(other station side)
Batch
DevLW(1) to DevLW(255)
Random
Direct link special relay
(other station side)
Batch
DevLSB(1) to DevLSB(255)
Random
Direct link special register
(other station side)
Batch
DevLSW(1) to DevLSW(255)
Random
Special direct buffer register
Batch
DevSPG(0) to DevSPG(255)
Random
Other station buffer memory
Batch
DevRBM
Random
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