RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 97 of 920
Dec 22, 2016
CHAPTER 6 CLOCK GENERATOR
For details about the clock generator for the RF transceiver, see 2.4 Base Operation Clock of RF Unit.
6.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of f
X = 1 to 20 MHz by connecting a resonator to X1 pin and X2 pin.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of
the clock operation status control register (CSC)).
<2> High-speed on-chip oscillator (High-speed OCO)
The frequency at which to oscillate can be selected from among f
IH = 32 MHz/24 MHz/16 MHz/12
MHz/8 MHz/ 6 MHz/4 MHz/3 MHz/2 MHz/1 MHz (TYP.) by using the option byte (000C2H). After a
reset release, the CPU always starts operating with this high-speed on-chip oscillator clock.
Oscillation can be stopped by executing the STOP instruction or setting of the HIOSTOP bit (bit 0 of
the CSC register).
The frequency specified by using an option byte can be changed by using the high-speed on-chip
oscillator frequency select register (HOCODIV). For details about the frequency, see Figure 6 - 12
Format of High-speed on-chip oscillator frequency select register (HOCODIV).
An external main system clock (f
EX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An
external main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed on-
chip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
(2) Subsystem clock
• XT1 clock oscillator
This circuit oscillates a clock of f
XT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 pin and XT2 pin.
Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).
An external subsystem clock (f
EXS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An
external subsystem clock input can be disabled by the setting of the XTSTOP bit.
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