RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 766 of 920
Dec 22, 2016
23.4.2 When used as interrupt mode
Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD) by
using the option byte 000C1H.
The operation is started in the following initial setting state when the interrupt mode is set.
- Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level
register (LVIS))
- The initial value of the voltage detection level select register (LVIS) is set to 01H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 1 (voltage detection level: V
LVD).
• Operation in LVD interrupt mode
In interrupt mode (LVIMDS1 and LVIMDS0 = 0 and 1 in the option byte), the state of an internal reset by the
LVD is retained immediately after a reset until the supply voltage (V
DD) exceeds the voltage detection level
(VLVD). The LVD internal reset is released when the supply voltage (VDD) exceeds the voltage detection level
(V
LVD).
After the LVD internal reset is released, an interrupt request signal (INTLVI) by the LVD is generated when the
supply voltage (V
DD) exceeds the voltage detection level (VLVD). When the voltage falls, this LSI should be
placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal, before the
voltage falls below the operating voltage range defined in 31.4 AC Characteristics. When restarting the
operation, make sure that the operation voltage has returned within the range of operation.
Figure 23 - 5 shows the timing of the interrupt request signal generated in the LVD interrupt mode.
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