RL78/G1H CHAPTER 20 STANDBY FUNCTION
R01UH0575EJ0120 Rev. 1.20 Page 738 of 920
Dec 22, 2016
Figure 20 - 3 HALT Mode Release by Reset (2/2)
(3) When subsystem clock is used as CPU clock
Note For the reset processing time, see CHAPTER 21 RESET FUNCTION.
20.3.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock
before the setting was the main system clock.
Caution Because the interrupt request signal is used to clear the STOP mode, if the interrupt mask flag
is 0 (the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt
request signal is generated), the STOP mode is immediately cleared if set when the STOP
instruction is executed in such a situation.
Accordingly, once the STOP instruction is executed, the system returns to its normal
operating mode after the elapse of release time from the STOP mode.
The operating statuses in the STOP mode are shown below.
HALT instruction
Oscillates
Oscillation
stopped
Oscillates
Oscillation
stopped
Subsystem clock
(XT1 oscillation)
Status of CPU
Reset signal
Normal operation
(subsystem clock)
HALT mode
Reset
period
Normal operation mode
(high-speed on-chip
oscillator clock)
Starting XT1 oscillation is
specified by software.
Oscillation stabilization time
(check by using OSTC register)
Note
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