Renesas RL78/G1H - Procedure for Processing Errors that Occurred During UART (Uartq) Communication

RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 426 of 920
Dec 22, 2016
14.6.4 Procedure for processing errors that occurred during UART (UARTq)
communication
The procedure for processing errors that occurred during UART (UARTq) communication is described in Figures
14 - 88 and 14 - 89.
Figure 14 - 88 Processing Procedure in Case of Parity Error or Overrun Error
Figure 14 - 89 Processing Procedure in Case of Framing Error
Remark m: Unit number (m = 0, 1), n: Channel number (n = 2, 3), mn = 02, 03, 12, 13, q: UART number (q = 1, 3)
Software Manipulation Hardware Status Remark
Reads serial data register mn
(SDRmn)
The BFFmn bit of the SSRmn register is
set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register mn (SSRmn). Error type is identified and the read value
is used to clear error flag.
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Error flag is cleared. Error can be cleared only during reading,
by writing the value read from the SSRmn
register to the SIRmn register without
modification.
Software Manipulation Hardware Status Remark
Reads serial data register mn
(SDRmn).
The BFFmn bit of the SSRmn register is
set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register mn (SSRmn). Error type is identified and the read value
is used to clear error flag.
Writes serial flag clear trigger register mn
(SIRmn).
Error flag is cleared. Error can be cleared only during reading,
by writing the value read from the SSRmn
register to the SIRmn register without
modification.
Sets the STmn bit of serial channel stop
register m (STm) to 1.
The SEmn bit of serial channel enable
status register m (SEm) is set to 0 and
channel n stops operating.
Synchronization with other party of
communication
Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Sets the SSmn bit of serial channel start
register m (SSm) to 1.
The SEmn bit of serial channel enable
status register m (SEm) is set to 1 and
channel n is enabled to operate.