RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 191 of 920
Dec 22, 2016
7.6.5 Timer Interrupt and TOmn Pin Output at Operation Start
In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or
not to generate a timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn)
generation.
In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.
Figure 7 - 39 shows operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 7 - 39 Operation examples of timer interrupt at count operation start and TOmn output
(a) When MDmn0 is set to 1
(b) When MDmn0 is set to 0
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a
toggle operation.
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not
change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
Remark m: Unit number (m = 0), n: Channel number (n = 3)
TEmn
TOmn
INTTMmn
Count operation start
TCRmn
TEmn
TOmn
INTTMmn
Count operation start
TCRmn
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