RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 172 of 920
Dec 22, 2016
7.4 Basic Rules of Timer Array Unit
7.4.1 Basic rules of simultaneous channel operation function
When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly
counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
(1) Only an even channel (channel 0, 2) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 0 is set as a master channel, channel 1 or those that follow (channels 1, 2, 3) can be set as
a slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may
not be set.
Example: If channels 0 and 2 are set as master channels, channels 1 can be set as the slave channel of master
channel 0. Channel 3 cannot be set as the slave channel of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKSmn0, CKSmn1 bits (bit 15, 14 of timer mode register mn (TMRmn)) of the slave
channel that operates in combination with the master channel must be the same value as that of the master
channel.
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower
channels.
(8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel
as a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to
channels with lower channel numbers.
(9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other
higher master channel as a source clock.
(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the
channels in combination must be set at the same time.
(11) During the counting operation, a TSmn bit of a master channel or TSmn bits of all channels which are operating
simultaneously can be set. It cannot be applied to TSmn bits of slave channels alone.
(12) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in
combination must be set at the same time.
(13) CKm2/CKm3 cannot be selected while channels are operating simultaneously, because the operating clocks of
master channels and slave channels have to be synchronized.
(14) Timer mode register m0 (TMRm0) has no master bit (it is fixed as “0”). However, as channel 0 is the highest
channel, it can be used as a master channel during simultaneous operation.
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