RL78/G1H CHAPTER 12 WATCHDOG TIMER
R01UH0575EJ0120 Rev. 1.20 Page 276 of 920
Dec 22, 2016
12.4 Operation of Watchdog Timer
12.4.1 Controlling operation of watchdog timer
(1) When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1
(the counter starts operating after a reset release) (for details, see CHAPTER 26).
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see
12.4.2 and CHAPTER 26).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H)
(for details, see 12.4.3 and CHAPTER 26).
(2) After a reset release, the watchdog timer starts counting.
(3) By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and
before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
(4) After that, write the WDTE register the second time or later after a reset release during the window open
period. If the WDTE register is written during a window close period, an internal reset signal is generated.
(5) If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is
generated.
An internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the WDTE register
• If data other than “ACH” is written to the WDTE register
Caution 1.When data is written to the watchdog timer enable register (WDTE) for the first time after reset
release, the watchdog timer is cleared in any timing regardless of the window open time, as
long as the register is written before the overflow time, and the watchdog timer starts counting
again.
Caution 2. After “ACH” is written to the WDTE register, an error of up to 2 clocks (f
IL) may occur before
the watchdog timer is cleared.
Caution 3. The watchdog timer can be cleared immediately before the count value overflows.
WDTON Watchdog Timer Counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
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