RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 388 of 920
Dec 22, 2016
14.5.5 Slave reception
Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock
being input from another device.
Note 1. Because the external serial clock input to the SCK10, SCK21, and SCK30 pins is sampled internally and used, the
fastest transfer rate is f
MCK/6 [Hz].
Note 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the
electrical specifications (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remark fMCK: Operation clock frequency of target channel
3-Wire Serial I/O CSI10 CSI21 CSI30
Target channel Channel 2 of SAU0 Channel 1 of SAU1 Channel 2 of SAU1
Pins used SCK10, SI10 SCK21, SI21 SCK30, SI30
Interrupt INTCSI10 INTCSI21 INTCSI30
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate
Max. f
MCK/6 [Hz]
Notes 1, 2
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-reverse
• CKPmn = 1: Reverse
Data direction MSB or LSB first
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