RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 556 of 920
Dec 22, 2016
18.4.3 Baseband Interrupt
Table 18 - 4 shows the interrupt sources.
If one or more bits are “1” in interrupt source bits in the table enabled by baseband interrupt registers 0 to 2, INTOUT
pin outputs high level. If the all interrupt source bits are “0”, the pin outputs low level.
The polarity of INTOUT output can be changed by INTOUTSEL bit.
Note 1. CCA completion interrupt and CSMA-CA completion interrupt are switched by CCATINTSEL bit.
Note 2. See 18.4.4 (89) for setting condition of threshold level occurring receive level filter interrupt causing detection of no
communication state.
Note 3. Byte reception interrupt and automatic receive timeout interrupt are switched by TIMEOUTINTSEL bit.
Note 4. When the frame length is short and the frame has no address information or incomplete address information, address
filter interrupt might not occur and only frame receive completion occurs.
Table 18 - 4 Interrupt Sources List
Number Interrupt Name Interrupt Occurrence Condition
1 Timer compare 0 Interrupt request occurs when timer value matches timer compare 0 value
2 Timer compare 1 Interrupt request occurs when timer value matches timer compare 1 value
3 Timer compare 2 Interrupt request occurs when timer value matches timer compare 2 value
4 Frame transmit completion Interrupt request occurs when a frame transmission completes
However, interrupt request does not occur at transmit completion when
automatic ACK receive mode is enabled, if the transmit frame includes ACK
request. The interrupt request occurs at completion of ACK reception or ACK
receive timeout
5 Bank 0 transmit completion Interrupt request occurs when transmit RAM data transmission of bank 0
completes
6 Bank 1 transmit completion Interrupt request occurs when transmit RAM data transmission of bank 1
completes
7
CCA completion
Note 1
Interrupt request occurs when CCA sequence completes
8
CSMA-CA completion
Note 1
Interrupt request occurs when CSMA-CA sequence completes
9 Frame receive completion Interrupt request occurs when a frame reception completes
However, interrupt request does not occur at receive completion when
automatic ACK reply mode is enabled, if the receive frame includes ACK
request. The interrupt request occurs at completion of ACK reply
10 Bank 0 receive completion Interrupt request occurs when bank 0 of receive RAM becomes full
11 Bank 1 receive completion Interrupt request occurs when bank 1 of receive RAM becomes full
12 Start reception Interrupt request occurs when SFD is detected
13
Address filter
Note 4
Interrupt request occurs when address match is recognized
14 Receive overrun Interrupt request occurs in the following cases
- Receive RAM bank 0 status bit is kept 1 and data reception to receive RAM
bank 0 is started again
- Receive RAM bank 1 status bit is kept 1 and data reception to receive RAM
bank 1 is started again
15
Mode switch receive completion
Interrupt request occurs when a mode switch frame is received
16
Receive level filter
Note 2
Interrupt request occurs when a communication error occurs such as no signal
state during frame reception
17 Receive byte counts Interrupt request occurs when setting count of bytes are received
18 Frame length Interrupt request occurs when the frame length is received
19
Byte reception
Note 3
Interrupt request occurs for each receive byte data
20
Automatic receive timeout
Note
3
Interrupt request occurs when timeout occurs with no receive frame, if the
automatic receive timeout function is enabled
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