RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 207 of 920
Dec 22, 2016
7.8.4 Operation as input signal high-/low-level width measurement
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
register (ISC) to 1. In the following descriptions, read TImn as RxD0.
By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the
signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be
calculated by the following expression.
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error equivalent to one operation clock occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set
to 1 and the TImn pin start edge detection wait status is set.
When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be
measured) is detected, the counter counts up from 0000H in synchronization with the count clock. When the
valid capture edge (falling edge of the TImn pin input when the high-level width is to be measured) is detected
later, the count value is transferred to timer data register mn (TDRmn) and, at the same time, INTTMmn is
output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the
counter does not overflow, the OVF bit is cleared. The TCRmn register stops at the value “value transferred to
the TDRmn register + 1”, and the TImn pin start edge detection wait status is set. After that, the above operation
is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is
updated depending on whether the counter overflows during the measurement period. Therefore, the overflow
status of the captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
bit of the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two
or more overflows occur.
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the
CISmn1 and CISmn0 bits of the TMRmn register.
Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1
while the TEmn bit is 1.
CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured.
CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured.
Signal width of TImn input = Period of count clock
×
((10000H
×
TSRmn: OVF) + (Capture value of TDRmn + 1))
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