RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 364 of 920
Dec 22, 2016
14.5.2 Master reception
Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device.
Note Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the
electrical specifications (see CHAPTER 31
ELECTRICAL SPECIFICATIONS).
3-Wire Serial I/O CSI10 CSI20 CSI21 CSI30
Target channel Channel 2 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1 Channel 2 of SAU1
Pins used SCK10, SI10 SCK20, SI20 SCK21, SI21 SCK30, SI30
Interrupt INTCSI10 INTCSI20 INTCSI21 INTCSI30
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can
be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate
Note
Max. fCLK/4 [Hz]
Min. f
CLK/(2 × 2
15
× 128) [Hz] fCLK: System clock frequency
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-reverse
•CKPmn = 1: Reverse
Data direction MSB or LSB first
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