RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 402 of 920
Dec 22, 2016
14.5.7 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSIp) communication can be calculated by the following
expressions.
(1) Master
(2) Slave
Note The permissible maximum transfer clock frequency is f
MCK/6.
Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B
to 1111111B) and therefore is 0 to 127.
The operation clock (f
MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
(Transfer clock frequency) = {Operation clock (f
MCK
) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}
Note
[Hz]
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