RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 768 of 920
Dec 22, 2016
23.4.3 When used as interrupt and reset mode
Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH,
VLVDL) by using the option byte 000C1H.
The operation is started in the following initial setting state when the interrupt & reset mode is set.
- Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level
register (LVIS))
- The initial value of the voltage detection level select register (LVIS) is set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: V
LVDH).
• Operation in LVD interrupt & reset mode
In the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0), the state of an internal reset by LVD is
retained until the supply voltage (V
DD) exceeds the high-voltage detection level (VLVDH) after power is supplied.
The internal reset is released when the supply voltage (VDD) exceeds the high-voltage detection level (VLVDH).
An interrupt request signal by LVD (INTLVI) is generated and arbitrary save processing is performed when the
supply voltage (V
DD) falls below the high-voltage detection level (VLVDH). After that, an internal reset by LVD is
generated when the supply voltage (VDD) falls below the low-voltage detection level (VLVDL). After INTLVI is
generated, an interrupt request signal is not generated even if the supply voltage becomes equal to or higher
than the high-voltage detection voltage (V
LVDH) without falling below the low-voltage detection voltage (VLVDL).
To use the LVD reset & interrupt mode, perform the processing according to Figure 23 - 8 Setting Procedure
for Operating Voltage Check and Reset.
Figures 23 - 6 and 23 - 7 show the timing of the internal reset signal and interrupt signal generated in the LVD
interrupt & reset mode.
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