RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 184 of 920
Dec 22, 2016
7.6.2 TOmn Pin Output Setting
The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer
operation start.
Figure 7 - 34 Status Transition from Timer Output Setting to Operation Start
<1> The operation mode of timer output is set.
• TOMmn bit (0: Master channel output mode, 1: Slave channel output mode)
• TOLmn bit (0: Positive logic output, 1: Negative logic output)
<2> The timer output signal is set to the initial status by setting timer output register m (TOm).
<3> The timer output operation is enabled by writing 1 to the TOEmn bit (writing to the TOm register is
disabled).
<4> The port I/O setting is set to output (see 7.3.14 Registers controlling port functions of pins to be
used for timer I/O).
<5> The timer operation is enabled (TSmn = 1).
Remark m: Unit number (m = 0), n: Channel number (n = 3)
TCRmn
(Counter)
Timer alternate-function pin
Timer output signal
TOEmn
TOmn
Undefined value (FFFFH after reset)
Hi-Z
Write operation disabled period to TOmnWrite operation enabled period to TOmn
<1> Set TOMmn
Set TOLmn
<2> Set TOmn <3> Set TOEmn <4>, <5> <5>Timer operation startSet the port
to output
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