Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS
R01UH0575EJ0120 Rev. 1.20 Page 870 of 920
Dec 22, 2016
31.4 AC Characteristics
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel
number (n = 3))
(TA = ‒40 to +85 °C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle
(minimum instruction
execution time)
T
CY Main system
clock (f
MAIN)
operation
HS (high-speed main)
mode
2.7 V ≤ V
DD ≤ 3.6 V 0.03125 1 μs
2.4 V ≤ V
DD < 2.7 V 0.0625 1 μs
LS (low-speed main)
mode
1.8 V ≤ V
DD ≤ 3.6 V 0.125 1 μs
Subsystem clock (fSUB) operation 1.8 V ≤ VDD ≤ 3.6 V 28.5 30.5 31.3 μs
In the self-
programming
mode
HS (high-speed main)
mode
2.7 V ≤ V
DD ≤ 3.6 V 0.03125 1 μs
2.4 V ≤ V
DD < 2.7 V 0.0625 1 μs
LS (low-speed main)
mode
1.8 V ≤ V
DD ≤ 3.6 V 0.125 1 μs
External system clock
frequency
fEX 2.7 V ≤ VDD ≤ 3.6 V 1.0 20.0 MHz
2.4 V ≤ V
DD < 2.7 V 1.0 16.0 MHz
1.8 V ≤ V
DD < 2.4 V 1.0 8.0 MHz
f
EXS 32 35 kHz
External system clock
input high-level width,
low-level width
t
EXH,
t
EXL
2.7 V ≤ VDD ≤ 3.6 V 24 ns
2.4 V ≤ V
DD < 2.7 V 30 ns
1.8 V ≤ V
DD < 2.4 V 60 ns
t
EXHS,
t
EXLS
13.7 μs
TI03 input high-level
width, low-level width
t
TIH, tTIL 1/fMCK + 10 ns
TO03 output
frequency
fTO HS (high-speed main) mode 2.7 V ≤ VDD ≤ 3.6 V 8 MHz
2.4 V ≤ V
DD < 2.7 V 4 MHz
LS (low-speed main) mode 1.8 V ≤ V
DD ≤ 3.6 V 4 MHz
PCLBUZ0, PCLBUZ1
output frequency
f
PCL HS (high-speed main) mode 2.7 V ≤ VDD ≤ 3.6 V 8 MHz
2.4 V ≤ V
DD < 2.7 V 4 MHz
LS (low-speed main) mode 1.8 V ≤ V
DD ≤ 3.6 V 4 MHz
Interrupt input high-
level width, low-level
width
t
INTH,
t
INTL
INTP0, INTP4, INTP6, INTP7,
INTP9 to INTP11
1.8 V ≤ VDD ≤ 3.6 V 1 μs
RESET
low-level
width
t
RSL 10 μs

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English