RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 183 of 920
Dec 22, 2016
7.6 Channel Output (TOmn pin) Control
7.6.1 TOmn pin output circuit configuration
Figure 7 - 33 Output Circuit Configuration
The following describes the TOmn pin output circuit.
<1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m
(TOLm) is ignored and only INTTMmp (slave channel timer interrupt) is transmitted to timer output
register m (TOm).
<2> When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and
INTTMmp (slave channel timer interrupt) are transmitted to the TOm register.
At this time, the TOLm register becomes valid and the signals are controlled as follows:
When TOLmn = 0: Forward operation (INTTMmn → set, INTTMmp → reset)
When TOLmn = 1: Reverse operation (INTTMmn → reset, INTTMmp → set)
When INTTMmn and INTTMmp are simultaneously generated, (0% output of PWM), INTTMmp
(reset signal) takes priority, and INTTMmn (set signal) is masked.
<3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTMmp
(slave channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register
(TOmn write signal) becomes invalid.
When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.
To initialize the TOmn pin output level, it is necessary to set timer operation is stopped (TOEmn = 0)
and to write a value to the TOm register.
<4> While timer output is disabled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write
signal) becomes valid. When timer output is disabled (TOEmn = 0), neither INTTMmn (master
channel timer interrupt) nor INTTMmp (slave channel timer interrupt) is transmitted to the TOm
register.
<5> The TOm register can always be read, and the TOmn pin output level can be checked.
Remark m: Unit number (m = 0)
n: Channel number (n = 3 (n = 0, 2 for master channel))
p: Slave channel number (p = 3)
<1>
<2>
<5>
Internal bus
TOmn register
Set
Reset/toggle
TOmn pin
TOmn write signal
TOEmn
TOLmn
TOMmn
Interrupt signal of the slave channel
(INTTMmp)
Interrupt signal of the master channel
(INTTMmn)
<3>
<4>
Controller
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