RL78/G1H CHAPTER 30 INSTRUCTION SET
R01UH0575EJ0120 Rev. 1.20 Page 838 of 920
Dec 22, 2016
30.2 Operation List
Note 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no
data is accessed.
Note 2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is accessed by
an 8-bit instruction.
Note 3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Table 30 - 5 Operation List (1/18)
Instruction
Group
Mnemonic Operands Bytes
Clocks
Clocks
Flag
Note 1 Note 2
ZACCY
8-bit data
transfer
MOV r, #byte
21—
r
←
byte
PSW, #byte
33—
PSW
←
byte
×××
CS, #byte
31—
CS
←
byte
ES, #byte
21—
ES
←
byte
!addr16, #byte
41—
(addr16)
←
byte
ES:!addr16, #byte
52—
(ES, addr16)
←
byte
saddr, #byte
31—
(saddr)
←
byte
sfr, #byte
31—
sfr
←
byte
[DE+byte], #byte
31—
(DE + byte)
←
byte
ES:[DE+byte], #byte
42—
((ES, DE) + byte)
←
byte
[HL+byte], #byte
31—
(HL + byte)
←
byte
ES:[HL+byte], #byte
42—
((ES, HL) + byte)
←
byte
[SP+byte], #byte
31—
(SP + byte)
←
byte
word[B], #byte
41—
(B + word)
←
byte
ES:word[B], #byte
52—
((ES, B) + word)
←
byte
word[C], #byte
41—
(C+word)
←
byte
ES:word[C], #byte
52—
((ES, C) + word)
←
byte
word[BC], #byte
41—
(BC+word)
←
byte
ES:word[BC], #byte
52—
((ES, BC) + word)
←
byte
A, r
Note 3
11—
A
←
r
r, A
Note 3
11—
r
←
A
A, PSW
21—
A
←
PSW
PSW, A
23—
PSW
←
A
×××
A, CS
21—
A
←
CS
CS, A
21—
CS
←
A
A, ES
21—
A
←
ES
ES, A
21—
ES
←
A
A, !addr16
314
A
←
(addr16)
A, ES:!addr16
425
A
←
(ES, addr16)
!addr16, A
31—
(addr16)
←
A
ES:!addr16, A
42—
(ES, addr16)
←
A
A, saddr
21—
A
←
(saddr)
saddr, A
21—
(saddr)
←
A
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